Spice Modeling
JFETs are unique devices in several areas, one of which is extremely low gate leakage. The SPICE2 Shichman Hodges model does not account for this and therefore does not accurately model gate leakage without the addition of the [katex]G_{Min}[/katex] parameter. The leakage conductance SPICE value [katex]G_{Min}[/katex] can be modified separately, but unfortunately that impacts all models that utilize [katex]G_{Min}[/katex] in that given simulation, including other JFETs and diodes. The default value of [katex]G_{Min}[/katex] in SPICE2 is [katex]10^{-12}[/katex] Siemens. Document CTC-023 lists the InterFET SPICE models with the [katex]G_{Min}[/katex] values at the top of each geometry section. If modeling is needed without [katex]G_{Min}[/katex], please note that the JFET leakage will not be accurate.
Download the related SPICE models here:
- CTC-023 SPICE models – SPICE models summarized by Geometry.
- InterFET SPICE models – Sortable Excel file with InterFET SPICE models.
FET LTspice Modeling
Provided are links to JFET LTspice modeling recommendations and present JFET models in LTspice. LTspice is freeware computer software implementing a SPICE electronic circuit simulator, produced by semiconductor manufacturer Linear Technology, now part of Analog Devices. It is used in-house at Linear Technology for IC design and is the most widely distributed and used SPICE program in the industry.
The initial LTspice installation comes with a limited set of JFET models stored in a file called standard.jft, typically found at the locations below:
C:\Users\Username\Documents\LTspiceXVII\lib\cmp\standard.jft
/Users/Username/Library/Application Support/LTspice/Lib/cmp/standard.jft
Related Resources