Spice Modeling

The primary focus of SPICE modeling at InterFET is SPICE2 parameters which can be easily used with most industry SPICE simulators. The core reference for this material is “Semiconductor Device Modeling with SPICE” second edition, by Giuseppe Massobrio and Paolo Antognetti. Detailed information on InterFET JFET SPICE model calculations and equations can be found in the following InterFET CTC-36 document.
SPICE is the de facto standard for simulating circuit performance. An abundance of libraries are available, but many of them were derived from data sheets. Data sheets seldom define the product, and at best they offer minimum performance guarantees. InterFET realizes that SPICE modeling is a critical part of new product design, and we strive to give accurate JFET SPICE models verified with real world measurements. In addition, we provide edge case modeling in most cases to cover design verification over the JFETs low and high extremes.
The following table of parameters will input directly into a SPICE circuit file. Be aware that SPICE parameters for any semiconductor (JFETs included) are valid only for that manufacturer. Because of the variants in design, the product of one manufacturer seldom matches that of another. These models are offered only as a guide for use in circuit analysis. Once the SPICE model is generated, the model outputs should be verified with the actual measured values.

JFETs are unique devices in several areas, one of which is extremely low gate leakage. The SPICE2 Shichman Hodges model does not account for this and therefore does not accurately model gate leakage without the addition of the G_{Min} parameter. The leakage conductance SPICE value G_{Min} can be modified separately, but unfortunately that impacts all models that utilize G_{Min} in that given simulation, including other JFETs and diodes. The default value of G_{Min} in SPICE2 is 10^{-12} Siemens. Document CTC-023 lists the InterFET SPICE models with the G_{Min} values at the top of each geometry section. If modeling is needed without G_{Min}, please note that the JFET leakage will not be accurate.

Download the related SPICE models here:


FET LTspice Modeling

Provided are links to JFET LTspice modeling recommendations and present JFET models in LTspice. LTspice is freeware computer software implementing a SPICE electronic circuit simulator, produced by semiconductor manufacturer Linear Technology, now part of Analog Devices. It is used in-house at Linear Technology for IC design and is the most widely distributed and used SPICE program in the industry.

The initial LTspice installation comes with a limited set of JFET models stored in a file called standard.jft, typically found at the locations below:




/Users/Username/Library/Application Support/LTspice/Lib/cmp/standard.jft

InterFET recommends replacing this file with a more complete compilation of JFET models from a wide range of manufacturers. The following compilation of JFET models is sorted by part numbers and lists the manufacturer in the part name with a “-” suffix. When the model manufacturer is unknown a “-GEN” is listed for the generic part. All of the models from the original LTspice standard.jft file are included in this file.